Method and system for performing reverse play of sd mpeg video

ABSTRACT

One or more methods and systems to efficiently process MPEG video in order to perform a reverse play or slow rewind function are presented. The method reduces system bandwidth required to implement the reverse play function when SD MPEG video is received by the MPEG decoder. Furthermore, the method maximizes the use of memory resources when one or more video frame buffers are implemented. The system comprises a first subsystem feeding one or more sequences of frames (e.g., feeding sessions) to a second subsystem. The first subsystem defines a set of parameters that is used to determine the one or more feeding sessions provided to the second subsystem. The second subsystem subsequently decodes the one or more feeding sessions using the set of parameters such that the video may be displayed.

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BACKGROUND OF THE INVENTION

Various functionalities have been implemented in devices such as digitalset-top-boxes or personal video recorders (PVRs) in order toconveniently manipulate video data. PVRs allow a user to employ one ormore indexing techniques or trick modes that include fast forward, slowmotion, frame advance, and reverse play in order to provide a moredesirable viewing experience to a user. These trick modes may beincorporated in the processing of video data. However, some of thesetrick modes are not easily implemented when processing MPEG video.

PVRs and digital set-top-boxes may incorporate one or more MPEG videodecoders. These video decoders may be used to decode both HD andstandard definition (SD) MPEG video streams. However, during processingof HD MPEG video data, the MPEG video decoder typically employs memoryresources that are capable of implementing only three or four videoframe buffers. Likewise, the processing of SD MPEG video data is limitedto the use of the same number of video frame buffers used when HD MPEGis received—three of four video frame buffers. Unfortunately, using afew video frame buffers when performing trick function processing, suchas a reverse play or a slow rewind decode on an SD MPEG stream, requiresa significant amount of processing resources from the MPEG decoder. Whenusing only a few (i.e., three or four) video frame buffers, the totalnumber of frames processed by the MPEG decoder becomes relatively largewhen decoding a segment of a particular SD MPEG data stream. Hence, theprocessing load encountered by MPEG decoder may be significantlyundesirable.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with some aspects of the present invention asset forth in the remainder of the present application with reference tothe drawings.

BRIEF SUMMARY OF THE INVENTION

Aspects of the invention provide for a method and system to efficientlyprocess MPEG video to perform a reverse play or slow rewind function.The method reduces system bandwidth required to implement the reverseplay function when SD MPEG video is received by the MPEG decoder.Further, the method maximizes the use of memory resources when one ormore video frame buffers are implemented. The system comprises a firstsubsystem feeding one or more sequences of frames (e.g., feedingsessions) to a second subsystem. The first subsystem defines a set ofparameters that is used to determine the one or more feeding sessionsprovided to the second subsystem. The second subsystem subsequentlydecodes the one or more feeding sessions using the set of parameterssuch that the video may be displayed.

In one embodiment, the method of efficiently decoding MPEG video toimplement a reverse play or slow rewind function comprises receivingMPEG video, parsing the MPEG video data into segments, determining thetype of video received, generating one or more feeding sessions,characterizing the one or more feeding sessions using one or moreparameters, decoding the one or more feeding sessions into frames,storing the frames into a number of video frame buffers, wherein thevideo frame buffers occupy a memory space corresponding to the type ofvideo received.

In one embodiment, a method of efficiently decoding MPEG video bitstreams to implement a reverse play or slow rewind function comprisesdetermining the type of MPEG video received, and implementing a firstnumber of video frame buffers based on the type of MPEG video received.

In one embodiment, a system of efficiently decoding MPEG video bitstreams to implement a reverse play or slow rewind function comprises afirst digital logic circuitry, a first software module, a second digitallogic circuitry, and a second software module.

In one embodiment, a system of efficiently decoding MPEG video bitstreams to implement a reverse play or slow rewind function comprises afirst subsystem capable of generating one or more feeding sessions, anda second subsystem capable of decoding the one or more feeding sessionsreceived from the first subsystem.

In one embodiment, a method to reverse play MPEG video comprisesdetermining a first number of frames to be decoded in a feeding session,determining a second number of frames to be displayed in the feedingsession, determining a third number of reference frames to be displayedin the feeding session, and determining a fourth number of B frames tobe displayed in the feeding session.

These and other advantages, aspects, and novel features of the presentinvention, as well as details of illustrated embodiments, thereof, willbe more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an MPEG reverse play decode system inaccordance with an embodiment of the invention.

FIG. 2 is a relational block diagram illustrating 4 HD video framesoccupying the available memory space provided by the output memory shownin FIG. 1, in accordance with an embodiment of the invention.

FIG. 3 is a relational block diagram illustrating 20 SD video framesoccupying the available memory space provided by the output memory shownin FIG. 1, in accordance with an embodiment of the invention.

FIGS. 4A and 4B are operational flow diagrams illustrating a processused by the data feeder subsystem to implement a reverse play or slowrewind function when decoding MPEG video in accordance with anembodiment of the present invention.

FIG. 5 is an operational flow diagram illustrating the algorithm used bythe data feeder subsystem to implement a reverse play or slow rewindfunction when decoding MPEG video in accordance with an embodiment ofthe present invention.

FIG. 6 is an operational flow diagram illustrating an algorithm used bythe MPEG decoder subsystem to implement a reverse play or slow rewindfunction in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Aspects of the present invention may be found in a system and method toefficiently perform a reverse play function for MPEG video streams usingan MPEG video decoder in a HDTV or HD set-top-box. Aspects of thepresent invention improve system performance by reducing bandwidth andusing system resources, such as memory resources for example, moreefficiently during a SD MPEG video decoding operation. When SD MPEGvideo is received, the memory resources implement a maximum number ofvideo frame buffers. The system comprises a first subsystem feeding oneor more sequences of frames (feeding sessions) to a second subsystem.The first subsystem defines a set of parameters that is used todetermine the one or more feeding sessions provided to the secondsubsystem. The second subsystem subsequently decodes the one or morefeeding sessions using the set of parameters such that the video may bedisplayed. The MPEG video streams processed by the system described maycomprise MPEG I or MPEG II type of video streams, for example.

FIG. 1 is a block diagram of an MPEG reverse play decode system inaccordance with an embodiment of the invention. The MPEG reverse playdecode system comprises a data feeder subsystem 104, a MPEG decodersubsystem 112, and a MPEG processing memory 120. The data feedersubsystem (DFS) 104 comprises a data feeder 106 and a data feedersoftware module 108. The DFS 104 communicates to the MPEG decodersubsystem (MDS) 112. The MDS 112 comprises a MPEG decoder 114 and anMPEG decoder software module 116. The MDS 112 communicates with the MPEGprocessing memory 120 as shown. The MPEG processing memory 120 comprisesan input memory 124 and an output memory 128. The output memory 128functions as one or more video frame buffers used to store one or morevideo frames prior to displaying on a display. The input memory 124 andoutput memory 128 comprises non-overlapping portions or sections of theMPEG processing memory 120. In one embodiment, the MPEG processingmemory 120 comprises a random access memory (RAM).

In one embodiment, the data feeder subsystem 104 and MPEG decodersubsystem 112 is implemented using a system on chip (SOC). In anotherembodiment, the data feeder 106 and the MPEG decoder 114 is implementedusing a SOC. In either instance, the SOC may employ memory resourcesprovided by a unified memory architecture (UMA). The UMA allows the SOCas well as one or more other devices to access and utilize a commonmemory such as the MPEG processing memory 120 described in FIG. 1.

The data feeder subsystem (DFS) 104 is used to generate one or morefeeding sessions for a particular MPEG video segment or GOP. The datafeeder 106 parses the MPEG stream into segments, with each segmentstarting and including a single I frame. The segments may be describedas a Group of Pictures (GOP) comprising a single I frame. After thereceived MPEG stream is parsed into segments, each segment may becharacterized by one or more feeding sessions. The data feeder subsystem104 generates one or more feeding sessions that are fully defined by oneor more sets of “feeding session parameters” provided by the data feedersoftware module 108. The feeding sessions generated by the data feeder106 are transmitted to the MPEG decoder 114 by way of the input memory124. The input memory 124 stores the feeding sessions for subsequentprocessing by the MPEG decoder 114. A feeding session comprises, forexample, a sequence of frames that starts and includes a single I frame.It may be alternatively defined as, for example, a Group of Pictures(GOP) having only one I frame. The feeding session may generally involvea minimum number of frames necessary for a MPEG decoder 114 to properlydisplay a particular number of frames, given a maximum number of videoframe buffers available for use.

The data feeder 106 comprises hardware such as digital logic circuitryused to receive MPEG video data. The MPEG video data may be receivedfrom one or more storage media such as a magnetic hard drive or acompact disc. The data feeder 106 operates with the data feeder softwaremodule 108 to determine if the incoming MPEG video stream comprises anHD MPEG video stream or an SD MPEG video stream. The data feeder 106operates on the incoming MPEG video stream one segment at a time. Thedata feeder software module 108 comprises a set of computer instructionsor software resident in a data storage device within the DFS 104. Afteranalyzing the MPEG video stream, the DFS 104 operates on each MPEG videosegment such that one or more feeding sessions are generated. The one ormore feeding sessions are subsequently stored in the input memory 124.In addition, the DFS 104 transmits one or more parameters (i.e., such asthe number of frames to be decoded, the number of frames to bedisplayed, the number of B frames, and/or the number of referenceframes) to the MDS 112 in order to describe the feeding sessionsgenerated by the DFS 104. In one embodiment, the type or structure ofthe video stream to be decoded may be communicated to the MDS 112. Forexample, the DFS 104 may indicate that the video stream to be processedby the MPEG decoder subsystem 112 will be used to display an SDformatted picture. In another instance, the DFS 104 may communicate tothe MDS 112 that the video to be displayed comprises an HD type ofpicture. The type of picture to be displayed affects the number of framebuffers implemented in the output memory 128 of the MPEG processingmemory 120. Due to resolution requirements, processing HD frames willutilize a larger buffer space in memory compared to processing SDframes. As a consequence, the number of SD video frame buffersimplemented in the output memory 128 will be larger than the number ofHD video frame buffers implemented. In one embodiment, the number ofvideo frame buffers used is inversely proportional to the displayresolution of the video to be displayed. Hence, the number of videoframe buffers implemented in the output memory 128 is adjusted tomaximize memory space provided by the output memory 128.

The data feeder software module 108 is used to apply a first algorithmto the MPEG video stream that facilitates the generation of one or morefeeding sessions for the MPEG decoder subsystem 112. The one or morefeeding sessions generated by the data feeder 106 comprise one or moresequence of frames that are used by the MPEG decoder subsystem 112 toproperly display a number of frames. The number of frames displayed in afeeding session is limited by the number of video frame buffersimplemented. The data feeder software module 108 is used to determinethe values of one or more parameters used to define and generate the oneor more sequences of frames also known as feeding sessions. Thesefeeding sessions are subsequently decoded and displayed by the MPEGdecoder subsystem 112. These parameters will be termed feeding sessionparameters. The feeding session parameters M, N, Q, and R are defined asfollows:

M—frames to be decoded.

N—frames to be displayed.

Q—number of reference frames to be displayed.

R—number of B frames to be displayed.

C—number of frames until a reference frame is encountered. (Thisvariable is used by the data feeder algorithm to determine the feedingsession parameters M, N, Q, and R.)

As illustrated in FIG. 1, the DFS 104 bi-directionally communicates withthe MDS 112. One or more feeding session parameters, such as M, N, Q,and R are transmitted from the DFS 106 to the MDS 112. The MDS 112 mayacknowledge the receipt of such feeding session parameters.

Correspondingly, the MDS 112 comprises a MPEG decoder 114 and a MPEGdecoder software module 116. The MPEG decoder software module 108applies a second algorithm to the one or more feeding sessions providedby the input memory 124 of the MPEG processing memory 120. The MPEGdecoder 114 operates with the MPEG decoder software module 116 toappropriately decode the one or more feeding sessions stored in theinput memory 124. The MPEG decoder 114 comprises hardware such as adigital logic circuitry. The input memory 124 stores one or more feedingsessions generated by the DFS 104. After receiving the one or morefeeding sessions, the MPEG decoder 114 properly stores decoded videoframes within output memory 128 for displaying to a display. As shown inFIG. 1, the MPEG decoder 114 transmits decoded video frames to theoutput memory 128. The MPEG decoder software module 116 comprises a setof computer instructions or software, resident in a data storage devicewithin the MDS 112, capable of implementing the second algorithmrequired to properly process the one or more MPEG video feeding sessionsprovided by the DFS 104. The MPEG decoder 114 bi-directionallycommunicates with the output memory 128 in order to properly decodesuccessive frames as well as store decoded frames that will be displayedon a display. The output memory 128 subsequently transmits the videoframes to the display. It is contemplated that one or more timingsignals and/or control signals may be used to appropriately transmit thedecoded video frames from the output memory 128 to the display.

FIG. 2 is a relational block diagram illustrating 4 HD video framesoccupying the available memory space provided by the output memory shownin FIG. 1, in accordance with an embodiment of the invention. When thedata feeder and data feeder software determine that the received MPEGvideo data comprises HD MPEG video, the output memory provides anavailable memory space capable of accommodating a maximum of 4 HD videoframes. As shown in FIG. 2, the available memory space may be configuredinto a maximum of 4 identically sized regions. Each of the four regionsrepresents one HD video frame buffer 204. There are a total of 4 HDvideo frame buffers that the output memory implements. The output memorythat is not occupied by a video frame buffer 204 is unusable memoryspace 208 resulting from differences in alignment of the HD video frameswithin the output memory space. In FIG. 2, the unusable memory space 208is depicted as a filled-in area.

FIG. 3 is a relational block diagram illustrating 20 SD video framesoccupying the available memory space provided by the output memory shownin FIG. 1, in accordance with an embodiment of the invention. In thisembodiment, when the data feeder and data feeder software determine thatthe received MPEG video data comprises SD MPEG video, the output memoryspace is configured to provide an available memory space capable ofaccommodating a maximum of 20 SD video frames. As shown in FIG. 3, theavailable memory space may be configured into a maximum of 20identically sized regions. Each region represents one SD video framebuffer 304. There are a total of 20 SD video frame buffers that theoutput memory implements. The output memory that is not occupied by avideo frame buffer 304 may comprise unusable memory space 308, 312resulting from differences in alignment of the SD video frames withinthe output memory space. In FIG. 3, the unusable memory space 308, 312is depicted as either crosshatched or filled-in areas. In thisembodiment, it is evident that the unusable memory space 308, 312exceeds the amount of unusable memory space illustrated in FIG. 2 by theamount shown in the cross-hatched area 308. No additional SD video framebuffers may be implemented because the unusable memory space 308, 312does not provide ample memory space. It is contemplated that in otherembodiments, the output memory may implement other than the exemplary 20SD video frame buffers described in the embodiment described previously.

FIGS. 4A and 4B are operational flow diagrams illustrating a processused by the data feeder subsystem to implement a reverse play or slowrewind function when decoding MPEG video in accordance with anembodiment of the present invention. At step 404, an MPEG video datasegment is received by the DFS where it is processed by the data feedersubsystem. The segment may be transmitted from a storage media such asan exemplary hard disk drive. The segment may be analyzed by the datafeeder software module and subsequently characterized in terms of anumber of parameters—M, N, Q, and R, whose definitions were providedearlier. At step 408, the type of MPEG video data received is determinedby the data feeder subsystem. In one embodiment, the type of MPEG videodata received comprises HD MPEG or SD MPEG video data. The type of MPEGvideo data received relates to the resolution of frames to be displayedon a display, monitor, or television. In one embodiment, receiving HDMPEG video data results in implementing 3 or 4 video frame buffers inthe output buffer of the MPEG processing memory (previously described inFIG. 1). In one embodiment, receiving SD MPEG video data results inimplementing an increased number of video frame buffers within theoutput memory of the MPEG processing memory. In one embodiment, thenumber of video frame buffers implemented in output memory of the MPEGprocessing memory is increased by a factor corresponding to the ratioequal to (HD frame resolution/SD frame resolution). A parameter T isused to define an integer number of video frame buffers implemented inthe output memory of the MPEG processing memory. (The parameter Tincludes a buffer within the output memory used in displaying theframes.) In one embodiment, a typical HD frame resolution corresponds to1920×1088 while a typical SD frame resolution corresponds to 720×480. Ifone assumes that the number of video frame buffers implemented for HDMPEG video data is four, a change in resolution from HD to that of SDresults in increasing the number of video buffers implemented in outputmemory from a value of T=4 to T=4×(1920×1088)/((720×480)=24. In anotherembodiment, T is equal to an integer value less than 24 because ofmemory alignment requirements as the number of video frame buffersincreases to 24. As a consequence, in one embodiment, T is equal to 20when the received MPEG video data segment corresponds to SD MPEG video.At step 412, the data feeder algorithm is applied to the MPEG video datasegment in order to determine M, N, Q, and R parameters thatcharacterize each feeding session. The algorithm initially sequentiallysearches for reference frames starting from the last frame of thesegment. The algorithm facilitates the generation of one or more feedingsessions. Each feeding session is characterized by a sequence of framesthat is processed by the MPEG decoder subsystem using the input andoutput memories of the MPEG processing memory. The algorithm providesfor an increased number of frame buffers when an SD MPEG video segmentis received. This allows for the efficient use of output memory in theMPEG processing memory. During the search routine, a frame in thesegment may be marked as a starting point for a subsequent search. Thestarting point defines the last frame of the next feeding session. Theone or more feeding sessions are used to populate the video framebuffers implemented within the output memory. At step 416, the datafeeder algorithm is applied recursively to the segment until the firstframe of the segment is reached. (The data feeder algorithm will bedescribed in greater detail with reference to FIG. 5.) Referring to step420, the data feeder algorithm analyzes the segment during its searchprocess to determine if N+C>T. If this condition is met, the startingframe of the next feeding session may be marked. At step 424, the datafeeder algorithm generates the sequence of frames within the feedingsession by way of the feeding session parameters (M, N, Q, and R) it hasdetermined. At step 428, the feeding session parameters are transmittedto the MPEG decoder subsystem (MDS). The MDS will use the feedingsession parameters in order to properly decode the feeding sessionsreceived by the DFS. At step 432, the frames of the feeding session areinput into the input memory of the MPEG processing memory. Next, at step436, if the search routine of the last feeding session is completed, theprocess ends. Otherwise, the process reverts back to step 412, where thenext feeding session is searched beginning at its marked starting point.

FIG. 5 is an operational flow diagram illustrating the algorithm used bythe data feeder subsystem to implement a reverse play or slow rewindfunction when decoding MPEG video in accordance with an embodiment ofthe present invention. As shown, the algorithm is used to determine thefeeding session parameters. At step 504, the feeding session parameters,M, N, Q, R, and C are set to zero. T, the number of video frame buffersimplemented in output memory, is determined by the data feeder subsystemas previously mentioned. At step 508, a received MPEG video data segmentis searched for reference frames starting from the last frame in thesegment. C is defined as the number of frames passed until a referenceframe is encountered. In one embodiment, the reference frames comprise Por I frames. At step 512, the equation N+C<T is evaluated. If N+C isless than T, the process continues at step 516. At step 516, theparameters or variables M and N are incremented by C. The parameter orvariable Q is incremented by one. The parameter or variable R isincremented by C and decremented by one. The defining equations areshown in FIG. 5, step 516. Next, the process proceeds to step 520, wherean evaluation is made whether the first frame has been reached. If thefirst frame is reached, the algorithm ends. However, if the first frameof the segment is not reached, the process reverts to step 508, in whichthe next reference frame is sought. C is determined and the processcontinues at step 512. If N+C is not less than T, the process continuesat step 524, where the starting point of the next feeding session ismarked. At step 528, M is incremented by one. Then, at step 532, anevaluation is made whether the first frame has been reached in thesegment. If the first frame has been reached, the process ends.Otherwise, the process continues at step 536. At step 536, the algorithmsearches for the next reference frame and tabulates the number offrames, C, until another reference frame is encountered. Thereafter, theprocess reverts to step 528, in which M is incremented by one. Again, atstep 532, the process continues until the first frame is reached.

The algorithm described in FIG. 5 may be used to determine the feedingsession parameters of one or more feeding sessions. In order toillustrate an application of the data feeder algorithm, the reader mayrefer to the following first example. The first example illustrates thefollowing exemplary segment received by the data feeder subsystem:

EXAMPLE 1

I0, P3, B1, B2, P6, B4, B5, P9, B7, B8, P12, B10, B11, P15, B13, B14.The segment contains a total of 16 frames. There are a total of 10 Bframes.

If we use the sample segment provided by Example 1, wherein the receivedbit stream or MPEG video data segment is a HD stream and an exemplary 4video frame buffers (T=4) are available to the MPEG decoder, the feedingsession parameters and feeding session may be determined using thealgorithm illustrated in FIG. 5 as shown below.

Feeding Session 1: Feed I0, P3, P6, P9, P12, P15, B13, B14 and instructthe MPEG decoder to decode 8 frames and display 3 frames, including 1reference frames and 2 B frames. The frames P15, B14, B13 are read outfrom the output memory into a display. The feeding session parametersare as follows: M=8, N=3, Q=1, and R=2.

Feeding Session 2: Feed I0, P3, P6, P9, P12, B10, B11, and instruct theMPEG decoder to decode 7 frames and display 3 frames, including 1reference frame and 2 B frames. The frames P12, B11, B10 are read outfrom the output memory into a display. The feeding session parametersare as follows: M=7, N=3, Q=1, and R=2.

Feeding Session 3: Feed I0, P3, P6, P9, B7, B8, and instruct the MPEGdecoder to decode 6 frames and display 3 frames, including 1 referenceframe and 2 B frames. The frames P9, B8, B7 are read out from the outputmemory into a display. The feeding session parameters are as follows:M=6, N=3, Q=1, and R=2.

Feeding Session 4: Feed I0, P3, P6, B4, B5, and instruct the MPEGdecoder to decode 5 frames and display 3 frames, including 1 referenceframe and 2 B frames. The frames P6, B5, B4 are read out from the outputmemory into a display. The feeding session parameters are as follows:M=5, N=3, Q=1, and R=2.

Feeding Session 5: Feed I0, P3, B1, B2, and instruct the MPEG decoder todecode and display 4 frames, including 2 reference frames and 2 Bframes. The frames P3, B2, B1 are read out from the output memory into adisplay. The feeding session parameters are as follows: M=4, N=3, Q=1,and R=2.

Feeding Session 6: Feed I0, and instruct the MPEG decoder to display I0.The feeding session parameters are as follows: M=1, N=1, Q=1, and R=0.

If the bit stream is SD, 20 video frame buffers are now available to theMPEG Decoder, and as a result, only one feeding session is required:

Feeding Session 1: Feed I0, P3, B1, B2, P6, B4, B5, P9, B7, B8, P12,B10, B11, P15, B13, B14. One may instruct the Mpeg Decoder that 16pictures are expected to be displayed, including 10 B pictures and 6reference pictures. The frames P15, B14, B13, P12, B11, B10, P9, B8, B7,P6, B5, B4, P3, B2, B1, I0 are read out from the output memory into adisplay. The feeding session parameters are as follows: M=16, N=16, Q=6,and R=10.

Example 1 clearly illustrates that the decoding requirement has beenreduced from decoding a total of 31 frames to that of decoding a totalof only 16 frames when the number of video frame buffers is increasedfrom 4 to 20. Hence, the processing bandwidth is reduced. In addition,the load generated by the data feeder subsystem is similarly reducedfrom that of storing 31 frames to that of storing only 16 frames intoinput memory of the MPEG processing memory. In the case of Example 1,the reduction in load corresponds to 15/31 or 48%.

In order to further illustrate the application of the data feederalgorithm, the reader may refer to the following second exampleillustrating the following exemplary segment received by the data feedersubsystem:

EXAMPLE 2

I0, P3, B1, B2, P6, B4, B5, P9, B7, B8, P12, B10, B11, P15, B13, B14,P18, B16, B17, P21, B19, B20, P24, B22, B23, P27, B25, B26, P30, B28,B29. This exemplary segment contains a total of 31 frames. There are atotal of 20 B frames.

If we use the sample segment provided by Example 2, wherein the receivedbit stream or MPEG video data segment is a HD stream, and an exemplary 4video frame buffers are available to the MPEG decoder, a total of elevenfeeding sessions are required.

However, if we use the sample segment provided by Example 2, wherein thereceived bit stream is a SD stream and an exemplary 20 video framebuffers are available to the MPEG decoder, the feeding sessions areimplemented as shown below.

Feeding Session 1: Feed I0, P3, P6, P9, P12, P15, B13, B14, P18, B16,B17, P21, B19, B20, P24, B22, B23, P27, B25, B26, P30, B28, B29.Instruct the MPEG decoder to decode 23 frames and display 18 frames,including 12 B frames and 6 reference frames. The frames P30, B29, B28,P27, B26, B25, P24, B22, B23, P21, B20, B19, P18, B17, B16, P15, B14,B13 are read out from the output memory into a display. The feedingsession parameters are as follows: M=23, N=18, Q=6, and R=12.

Feeding session 2: Feed I0, P3, B1, B2, P6, B4, B5, P9, B7, B8, P12,B10, B11. Instruct the MPEG decoder to decode and display 13 frames,including 8 B pictures and 5 reference pictures. The frames P12, B11,B10, P9, B8, B7, P6, B5, B4, P3, B2, B1, I0 are read out from the outputmemory into a display. The feeding session parameters are as follows:M=13, N=13, Q=5, and R=8.

FIG. 6 is an operational flow diagram illustrating an algorithm used bythe MPEG decoder subsystem to implement a reverse play or slow rewindfunction in accordance with an embodiment of the present invention. TheMPEG decoder algorithm is executed by way of the MPEG decoder operatingwith the MPEG decoder software module. The MPEG decoder software moduleexecutes a set of computer instructions or software capable ofimplementing the MPEG decoder algorithm. At step 604, the MPEG decoderalgorithm allocates the first R video frame buffers to all B frames in aparticular feeding session. As described earlier, one or more feedingsessions are transmitted by the DFS to the input memory of the MPEGprocessing memory. As was described earlier, there are a total of Tvideo frame buffers implemented in the output memory of the MPEGprocessing memory. At step 608, the next (T−R−1) video frame buffers areallocated to (M−R) reference frames. (Aspects of the present inventionallocate one video frame buffer in the output memory for displaying thedecoded frames; as a consequence, the number of available video framebuffers available for use by the MPEG decoder subsystem is reduced byone.) Then at step 612, decoding by the MPEG decoder commences. At step616, the MPEG decoder algorithm assesses whether the value (T−R−1) isless than the value (M−R). If (T−R−1) is less than (M−R), the processcontinues with step 620. At step 620, (M−T+1) reference frames in theoutput memory are discarded after being used by the MPEG decoder.Thereafter, the next (M−T+1) reference frames are allocated into theoutput memory for subsequent decoding by the MPEG decoder. The processproceeds to step 624, where the contents of the output memory aredisplayed after the (M−T+1) frames are utilized and all decodingprocesses are completed by the MPEG decoder. Step 616 determines whetherthe remaining video frame buffers are sufficient to hold the referenceframes to be decoded. If the remaining video frame buffers aresufficient to hold the (M−R) reference frames (when (T−R−1) is not lessthan (M−R)), the process continues with step 624. At step 624, theframes stored or allocated in the video frame buffers are subsequentlydisplayed from memory after the decoding of the feeding session iscompleted. After displaying is completed, another cycle of the MPEGdecoder algorithm may commence with the next feeding session.

An example will be used to illustrate the MPEG decoder algorithm. If oneuses the first feeding session of Example 2, the data feeder subsystemwill transmit the feeding session parameters, M, N, Q, R, and T to theMPEG decoder subsystem. For the first feeding session, M=23, N=18, Q=6,R=12, and T=20. In other words, 23 frames are to be decoded and 18frames are expected to be displayed. 6 reference frames and 12 B framesare expected to be displayed. The number of video frame buffersimplemented in output memory is 20. The MPEG decoder allocates the first12 video frame buffers to all of the B frames. The remaining 7 videoframe buffers (denoted as Rf1, Rf2, . . . Rf7) will be allocated to holdthe reference frames.

The feeding order or sequence of frames in the first feeding session is:I0, P3, P6, P9, P12, P15, B13, B14, P18, B16, B17, P21, B19, B20, P24,B22, B23, P27, B25, B26, P30, B28, B29.

The MPEG decoder will allocate the decoded frames into the frame buffersas follows: I0 −> Rf1 P3 −> Rf2 P6 −> Rf3 P9 −> Rf4 P12 −> Rf5 P15 −>Rf6 P18 −> Rf7 P21 −> Rf1 P24 −> Rf2 P27 −> Rf3 P30 −> Rf4

As illustrated above, frames I0, P3, P6, and P9 are discarded such thatframes P21, P24, P27, and P30 may be stored in the output memory of theMPEG processing memory. After decoding is completed, the contents ofoutput memory may be read out to a display.

While the invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the invention without departing from its scope.Therefore, it is intended that the invention not be limited to theparticular embodiment disclosed, but that the invention will include allembodiments falling within the scope of the appended claims.

1-38. (canceled)
 39. A system for efficiently decoding MPEG video toimplement a reverse play or slow rewind function comprising: at leastone circuitry for: receiving said MPEG video; determining the type ofsaid MPEG video received; arranging a portion of said MPEG videoreceived into one or more sequences of frames; characterizing each ofsaid one or more sequences of frames using one or more parameters;decoding said one or more sequences of frames based on said one or moreparameters; and storing said frames into a number of video framebuffers, said number of video frame buffers implemented based on saidtype of said MPEG video received.
 40. The system of claim 39 whereineach of said one or more sequences of frames comprises a feedingsession.
 41. The system of claim 40 wherein said feeding session isstored into a first portion of memory.
 42. The system of claim 41wherein said memory comprises a random access memory.
 43. The system ofclaim 39 wherein said at least one circuitry is used for displaying saidframes from said video frame buffers onto a display.
 44. The system ofclaim 43 wherein said video frame buffers are implemented in a secondportion of memory.
 45. The system of claim 44 wherein said memorycomprises a random access memory (RAM).
 46. The system of claim 39wherein said type of MPEG video comprises high definition (HD) orstandard definition (SD).
 47. The system of claim 39 wherein said MPEGvideo comprises MPEG I or MPEG II video.
 48. The system of claim 39wherein said number of video frame buffers implemented is inverselyproportional to frame resolution.
 49. The system of claim 39 whereinsaid number of video frame buffers is increased by the ratio(1920×1088)/(720×480) when said type of video received corresponds to SDMPEG video.
 50. The system of claim 39 wherein said at least onecircuitry is used for parsing said MPEG video into one or more segmentsprior to said arranging, each of said one or more segments comprisingone or more frames, wherein only the first frame of each of said one ormore segments is an I frame.
 51. A system for efficiently decoding MPEGvideo bit streams, comprising: at least one circuitry for: determiningthe type of MPEG video received; and implementing a first number ofvideo frame buffers based on said type of MPEG video received, saiddecoding performed to implement a reverse play or slow rewind function.52. The system of claim 51 wherein said at least one circuitry is usedfor generating one or more feeding sessions based on said first numberof video frame buffers.
 53. The system of claim 52 wherein a secondnumber of frames displayed in each of said one or more feeding sessionsis limited to said first number of video frame buffers.
 54. The systemof claim 53 wherein each of said one or more feeding sessions comprisesa minimum number of I, P, and B frames required to adequately decode anddisplay said second number of frames.
 55. The system of claim 51 whereinsaid implementing a number of video frame buffers maximizes the use ofan available memory space.
 56. The system of claim 51 wherein said typeof MPEG video received comprises high definition (HD) or standarddefinition (SD).
 57. The system of claim 52 wherein an algorithm is usedto determine one or more parameters that define said one or more feedingsessions.
 58. The system of claim 57 wherein said one or more parameterscomprises a first number of frames to be decoded, a second number offrames to be displayed, a third number of reference frames to bedisplayed, and a fourth number of B frames to be displayed.